Article:		Black Box with a View, Part 2
Subject:		timing
Date:		2006-03-01 10:39:07
From:		georgebelotsky
Response to: timing
Actually, timera.h looks correct. 3 << 6 = 0xC0 = 0x80 + 0x40 ... which is bits 7 and 6 set </pre> From page 11-20 of the MSP430x1xx Family User's Guide , the IDx bits (which control input clock divider) are 7 and 6 -- if both are set, the clock is divided by 8. Also, several of TI's code examples -- such as fet140_ta_09.c -- illustrates the use of the ACLK with an HF crystal. Best Wishes, George.

Showing messages 1 through 3 of 3.

• timing
  2006-03-01 11:58:52  bartvan deenen [View]
  
  
  Huh, the User Guide shows on page 4-15 the DIVAx bits of BCSCTL1 to be bits 4 and 5
• timing
  2006-03-01 12:00:52  bartvan deenen [View]
  
  
  Oh I see
  I was dividing the ACLK, and there is another divider for Timer A. Complicated all these timers.
  
  
• timing
  2006-03-01 18:11:06  georgebelotsky [View]
  
  
  Yes, configuring the hardware can be error prone.
  
  Particularly, watch out for the convenience macros that define symbolic names for various bits. The macros are helpful, but there is nothing to prevent you applying them to the wrong register.
  
  Try TI's examples as a starting point when dealing with MSP430 features that are new to you. You can be reasonably sure that they are setting up the microcontroller correctly.
  
  Get the example to run first, then use it as a guide to build your own device driver for the hardware in question.
  
  Best Wishes,
  
  George.